The 74HC74 devices contain two independent D-type positive-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of CLK. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.<br><br><b>Juried Engineering Products are shipped in ESD Safe Packaging and are Authentic/Genuine Components.</b>
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Juried Engineering SN74HC74N Dual D-Type Positive-Edge-Triggered Flip-Flops with Clear and Preset Breadboard-Friendly (1 Piece)
Brand: Juried Engineering
The 74HC74 devices contain two independent D-type positive-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of CLK. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.
Details
- Wide Operating Voltage Range: 2 V to 6 V
- Outputs Can Drive Up To 10 LSTTL Loads
- Low Power Consumption, 40-µA Maximum ICC
- Typical tpd = 15 ns, ±4-mA Output Drive at 5 V
- Very Low Input Current of 1 µA
Juried Engineering SN74HC74N Dual D-Type Positive-Edge-Triggered Flip-Flops with Clear and Preset Breadboard-Friendly (Pack of 10)
Brand: Juried Engineering
The 74HC74 devices contain two independent D-type positive-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of CLK. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.
Details
- Wide Operating Voltage Range: 2 V to 6 V
- Outputs Can Drive Up To 10 LSTTL Loads
- Low Power Consumption, 40-µA Maximum ICC
- Typical tpd = 15 ns, ±4-mA Output Drive at 5 V
- Very Low Input Current of 1 µA
Juried Engineering SN74HC74N Dual D-Type Positive-Edge-Triggered Flip-Flops with Clear and Preset Breadboard-Friendly (Pack of 5)
Brand: Juried Engineering
The 74HC74 devices contain two independent D-type positive-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of CLK. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.
Details
- Wide Operating Voltage Range: 2 V to 6 V
- Outputs Can Drive Up To 10 LSTTL Loads
- Low Power Consumption, 40-µA Maximum ICC
- Typical tpd = 15 ns, ±4-mA Output Drive at 5 V
- Very Low Input Current of 1 µA
Juried Engineering SN74HC74N 74HC74 Dual D-Type Positive-Edge-Triggered Flip-Flops with Clear and Preset Breadboard-Friendly IC DIP-14 (Pack of 5)
Brand: Juried Engineering
The SN74HC74 devices contain two independent D-type positive-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of CLK. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.
Details
- The SN74HC74 devices contain two independent D-type positive-edge-triggered flip-flops
- Wide Operating Voltage Range: 2 V to 6 V
- Outputs Can Drive Up To 10 LSTTL Loads
- Low Power Consumption, 40-µA Maximum ICC
- Typical tpd = 15 ns, ±4-mA Output Drive at 5 V, Very Low Input Current of 1 µA
Juried Engineering SN74HC74N 74HC74 Dual D-Type Positive-Edge-Triggered Flip-Flops with Clear and Preset Breadboard-Friendly IC DIP-14 (1 Piece)
Brand: Juried Engineering
The SN74HC74 devices contain two independent D-type positive-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of CLK. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.
Details
- The SN74HC74 devices contain two independent D-type positive-edge-triggered flip-flops
- Wide Operating Voltage Range: 2 V to 6 V
- Outputs Can Drive Up To 10 LSTTL Loads
- Low Power Consumption, 40-µA Maximum ICC
- Typical tpd = 15 ns, ±4-mA Output Drive at 5 V, Very Low Input Current of 1 µA