Juried Engineering . CD4043BE
Attributes
Distributor offers
| Seller | SKU | MOQ | In stock | Multiple | Prices |
|---|---|---|---|---|---|
| AmazonSC | B011NAV9NC | 1 | 1 |
Related on Amazon
As an Amazon Associate, we earn from qualifying purchases. (paid link) CERTAIN CONTENT THAT APPEARS ON THIS SITE COMES FROM AMAZON. THIS CONTENT IS PROVIDED 'AS IS' AND IS SUBJECT TO CHANGE OR REMOVAL AT ANY TIME.
Juried Engineering CD4043BE CD4043 CD4043 CMOS Quad NOR R/S Latch with 3-State Outputs Breadboard-Friendly IC DIP-16 (Pack of 10)
Brand: Juried Engineering
The CD4043B types are quad cross-coupled 3-state CMOS NOR latches. Each latch has a separate Q output and individual SET and RESET inputs. The Q outputs are controlled by a common ENABLE input. A logic "1" or high on the ENABLE input connects the latch states to the Q outputs. A logic "0" or low on the ENABLE input disconnects the latch states from the Q outputs, resulting in an open circuit condition on the Q outputs. The open circuit feature allows common busing of the outputs.
Details
- The CD4043B types are quad cross-coupled 3-state CMOS NOR latches. Each latch has a separate Q output and individual SET and RESET inputs.
- 3-state outputs with common output ENABLE, 5-V, 10-V, and 15-V parametric ratings, Noise margin (over full package temperature range): 1 V at VDD = 5 V, 2 V at VDD = 10 V, 2.5 V at VDD = 15 V
- Separate SET and RESET inputs for each latch, Standardized symmetrical output characteristics, Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"
- NOR and NAND configurations, 100% tested for quiescent current at 20 V, Maximum input current of 1 µA at 18 V over full package temperature range; 100 nA at 18 V and 25°C
- Example Applications: Holding register in multi-register system, Four bits of independent storage with output ENABLE, Strobed register, General digital logic
Juried Engineering CD4043BE CD4043 CD4043 CMOS Quad NOR R/S Latch with 3-State Outputs Breadboard-Friendly IC DIP-16 (1 Piece)
Brand: Juried Engineering
The CD4043B types are quad cross-coupled 3-state CMOS NOR latches. Each latch has a separate Q output and individual SET and RESET inputs. The Q outputs are controlled by a common ENABLE input. A logic "1" or high on the ENABLE input connects the latch states to the Q outputs. A logic "0" or low on the ENABLE input disconnects the latch states from the Q outputs, resulting in an open circuit condition on the Q outputs. The open circuit feature allows common busing of the outputs.
Details
- The CD4043B types are quad cross-coupled 3-state CMOS NOR latches. Each latch has a separate Q output and individual SET and RESET inputs.
- 3-state outputs with common output ENABLE, 5-V, 10-V, and 15-V parametric ratings, Noise margin (over full package temperature range): 1 V at VDD = 5 V, 2 V at VDD = 10 V, 2.5 V at VDD = 15 V
- Separate SET and RESET inputs for each latch, Standardized symmetrical output characteristics, Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"
- NOR and NAND configurations, 100% tested for quiescent current at 20 V, Maximum input current of 1 µA at 18 V over full package temperature range; 100 nA at 18 V and 25°C
- Example Applications: Holding register in multi-register system, Four bits of independent storage with output ENABLE, Strobed register, General digital logic
Juried Engineering CD4043BE CD4043 CD4043 CMOS Quad NOR R/S Latch with 3-State Outputs Breadboard-Friendly IC DIP-16 (Pack of 20)
Brand: Juried Engineering
The CD4043B types are quad cross-coupled 3-state CMOS NOR latches. Each latch has a separate Q output and individual SET and RESET inputs. The Q outputs are controlled by a common ENABLE input. A logic "1" or high on the ENABLE input connects the latch states to the Q outputs. A logic "0" or low on the ENABLE input disconnects the latch states from the Q outputs, resulting in an open circuit condition on the Q outputs. The open circuit feature allows common busing of the outputs.
Details
- The CD4043B types are quad cross-coupled 3-state CMOS NOR latches. Each latch has a separate Q output and individual SET and RESET inputs.
- 3-state outputs with common output ENABLE, 5-V, 10-V, and 15-V parametric ratings, Noise margin (over full package temperature range): 1 V at VDD = 5 V, 2 V at VDD = 10 V, 2.5 V at VDD = 15 V
- Separate SET and RESET inputs for each latch, Standardized symmetrical output characteristics, Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"
- NOR and NAND configurations, 100% tested for quiescent current at 20 V, Maximum input current of 1 µA at 18 V over full package temperature range; 100 nA at 18 V and 25°C
- Example Applications: Holding register in multi-register system, Four bits of independent storage with output ENABLE, Strobed register, General digital logic
Juried Engineering CD4043BE CD4043 CD4043 CMOS Quad NOR R/S Latch with 3-State Outputs Breadboard-Friendly IC DIP-16 (Pack of 5)
Brand: Juried Engineering
The CD4043B types are quad cross-coupled 3-state CMOS NOR latches. Each latch has a separate Q output and individual SET and RESET inputs. The Q outputs are controlled by a common ENABLE input. A logic "1" or high on the ENABLE input connects the latch states to the Q outputs. A logic "0" or low on the ENABLE input disconnects the latch states from the Q outputs, resulting in an open circuit condition on the Q outputs. The open circuit feature allows common busing of the outputs.
Details
- The CD4043B types are quad cross-coupled 3-state CMOS NOR latches. Each latch has a separate Q output and individual SET and RESET inputs.
- 3-state outputs with common output ENABLE, 5-V, 10-V, and 15-V parametric ratings, Noise margin (over full package temperature range): 1 V at VDD = 5 V, 2 V at VDD = 10 V, 2.5 V at VDD = 15 V
- Separate SET and RESET inputs for each latch, Standardized symmetrical output characteristics, Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"
- NOR and NAND configurations, 100% tested for quiescent current at 20 V, Maximum input current of 1 µA at 18 V over full package temperature range; 100 nA at 18 V and 25°C
- Example Applications: Holding register in multi-register system, Four bits of independent storage with output ENABLE, Strobed register, General digital logic